VLSI UNIVERSE
Showing posts with label
asynchronous reset
.
Show all posts
Showing posts with label
asynchronous reset
.
Show all posts
Interview questions related to reset design and reset timing
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Below we list few of our posts related to reset timing and some design concepts related to reset. Happy learning. Reset basics - Disc...
Duty cycle care-abouts for clock paths in reset assertion
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In the post Asynchronous reset assertion timing scenarios , we discussed how we may need to time the assertion of asynchronous reset as we...
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Asynchronous reset assertion timing scenarios
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We have always heard that for asynchronous resets, only de-assertion needs to be timed. This is true for most of the designs as the guidel...
Synchronous and asynchronous resets
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In the post reset basics, we discussed the need of having reset and the strategies used by designers related to reset. One of the decision...
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