VLSI UNIVERSE

As discussed in clock gating - basics , enable signal coming in data path is transferred into clock path in order to save dynamic power. B...

Solution: The design in question is a combinatorial design with 32-bit input (given) and a 4-bit output as shown in figure 1 below. How th...

Solution: The design in question is a combinational design with 32-bit input and 6-bit output as there can be maximum 32 1's and 32 st...

Clock dividers are ubiquitous circuits used in every digital design. A divide-by-N divider produces a clock that is N times lesser frequen...

Problem statement: Develop a synthesizable C/C++ function which is capable of performing image filtering. The filtering operation is defin...

For instance, you will find technology nodes as 180 um 90 um, 65 um, 45 um, 32 um, 22 um and so on.. *Source - Digital integrated ci...

There can be 4 cases of latch-to-flop timing paths as discussed below: 1. Positive level-sensitive latch to positive edge-triggered regi...

Definition of a multiplexer : A 2^n-input mux has n select lines. It can be used to implement logic functions by implementing LUT (Look-Up...

Problem: 100 latches (either all positive or all negative) are placed in series (figure 1). How many cycles of latency will it introduce?...

2-input XOR gate using a 2:1 multiplexer : As we know, a 2:1 multiplexer selects between two inputs depending upon the value of its select...

Static timing analysis (STA) is an analysis method of computing the max/min delay values of a complete circuit without actually simulating...

Defining a clock signal in VHDL Clock is the backbone of any synchronous design. For test-benches, a clock is the most desired signal as...