VLSI UNIVERSE

PROBLEM: In the following figure, it is desired to toggle the select of the mux from CLOCK_DIV to CLOCK and both the clocks are running. W...

What is a half cycle path? A half cycle timing path is one in which launch and capture happen on different clock edges. A half cycle path...

One of the guys asked me a question, "Why is hold always checked on the same edge?" Normally, it is taught in books/colleges tha...

In our previous post, Setup and hold – the state machine perspective , we discussed how setup and hold can be defined in respect of state ...

A buffer is an element which produces an output signal, which is of the same value as the input signal. We can also refer a buffer as a re...

As we know that cell delay is a function of output load capacitance. The most simplistic equivalent circuit of a logic gate driving an out...

In our previous posts, we discussed about the duty cycle, duty cycle variation and duty cycle degradation. Bad duty cycle impacts half cyc...

Duty cycle : Duty cycle of a clock is defined as the fraction of a period of clock during which the clock is in active state. Duty cycle o...

Clock jitter : By definition, clock jitter is the deviation of a clock edge from its ideal position in time. Simply speaking, it is the ina...

First of all, we need to understand what is meant by jitter. In most simplistic language, jitter is the uncertainty of a clock source in p...

Recovery and removal checks are associated with deassertion of asynchronous reset. The assertion of reset causes the output to get reset a...

In the post clock switching and clock gating checks , we discussed how important it is to have a glitch free clock. Also, in clock gatin...

Problem : Figure 1 below shows a timing path from a positive edge-triggered flip-flop to a positive edge-triggered flip-flop. Considering ...

In the post  setup and hold time violations , we learnt about the setup time violations and hold time violations. In this post, we will le...

In the post setup and hold time violations , we learnt about the setup time violations and hold time violations. In this post, we will lea...