VLSI UNIVERSE

What is a half cycle path? A half cycle timing path is one in which launch and capture happen on different clock edges. A half cycle path...

A buffer is an element which produces an output signal, which is of the same value as the input signal. We can also refer a buffer as a re...

As we know that cell delay is a function of output load capacitance. The most simplistic equivalent circuit of a logic gate driving an out...

In our previous posts, we discussed about the duty cycle, duty cycle variation and duty cycle degradation. Bad duty cycle impacts half cyc...

Clock jitter : By definition, clock jitter is the deviation of a clock edge from its ideal position in time. Simply speaking, it is the ina...

Clock skew is one of the most important parameters of a good physical design implementation. Keeping the clock skew to a minimum is consi...

Static timing analysis (STA) is a vast domain involving many sub-fields. It involves computing the limits of delay of elements in the circ...