VLSI UNIVERSE
Showing posts with label
Low power design
.
Show all posts
Showing posts with label
Low power design
.
Show all posts
Can we use discrete latches and AND/OR gates instead of ICG?
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In the post, Integated Clock Gating Cell , we discussed that an ICG has a negative level-sensitive latch preceding an AND gate in order to...
Design problem: Clock gating for a shift register
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Problem : There is an 4-bit shift register with parallel read and write capability as shown in the diagram. We need to find out an opportun...
Power aware RTL design
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With the progress in technology, the designs are moving into deeper sub-micron technology nodes. There is an ever-increasing conc...
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