VLSI UNIVERSE
Showing posts with label
Digital system design
.
Show all posts
Showing posts with label
Digital system design
.
Show all posts
Divide by 2 clock in VHDL
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Clock dividers are ubiquitous circuits used in every digital design. A divide-by-N divider produces a clock that is N times lesser frequen...
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Delay line based Time to digital converter
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A time to digital converter is a circuit that digitizes time; i.e., it converts time into digital number. In other words, a time-to-digita...
How propagation of ‘X’ happens through different logic gates
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‘X’ refers to a signal attaining a value that is ‘unknown’. It can be either ‘0’ or ‘1’. But, the exact value of the signal is not known...
4 comments:
On-chip variations – the STA takeaway
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Static timing analysis of a design is performed to estimate its working frequency after the design has been fabricated. Nominal delays of ...
Latency and throughput – the two measures of system performance
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Performance of the system is one of the most stringent criteria for its success. While performance increases the desirability among custo...
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What is Logic Built-in Self Test (LBIST)
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LBIST stands for Logic Built-In Self Test. As VLSI marches to deep sub-micron technologies, LBIST is gaining importance due to the unique ...
Worst Slew Propagation
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Worst slew propagation is a phenomenon in Static Timing Analysis. According to it, the worst of the slews at the input pin of a gate is p...
Depletion MOSFET and negative logic. Why it is not possible?
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As we know, depletion MOSFET conducts current even with gate and source at same voltage level. To cut-off the current in depletion MOSFE...
Setup check and hold check for flop-to-latch timing paths
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In the post ( Setup and hold – basics of timinganalysis ), we introduced setup and hold timing requirements and also discussed why the...
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