VLSI UNIVERSE

As discussed in clock gating - basics , enable signal coming in data path is transferred into clock path in order to save dynamic power. B...

Solution: The design in question is a combinatorial design with 32-bit input (given) and a 4-bit output as shown in figure 1 below. How th...

Solution: The design in question is a combinational design with 32-bit input and 6-bit output as there can be maximum 32 1's and 32 st...

Synchronization questions is one of the favorites among VLSI job interviewers. This is because they check not just the general intellectua...

It is a very common requirement to detect either positive edge, negative edge or both edges of a signal. And the circuit that can detect a...

Below we list few of our posts related to clock jitter and duty cycle variation. Happy learning. Clock jitter : Disusses the definition...

In the post Asynchronous reset assertion timing scenarios , we discussed how we may need to time the assertion of asynchronous reset as we...

We have always heard that for asynchronous resets, only de-assertion needs to be timed. This is true for most of the designs as the guidel...

In the post, Integated Clock Gating Cell , we discussed that an ICG has a negative level-sensitive latch preceding an AND gate in order to...

Problem : There is an 4-bit shift register with parallel read and write capability as shown in the diagram. We need to find out an opportun...

A buffer is an element which produces an output signal, which is of the same value as the input signal. We can also refer a buffer as a re...

As we know that cell delay is a function of output load capacitance. The most simplistic equivalent circuit of a logic gate driving an out...

Hi friends, in the post State machines – a practical perspective , we learnt about state machines. We also discussed different aspects of ...

In the post clock switching and clock gating checks , we discussed how important it is to have a glitch free clock. Also, in clock gatin...

An 8x1 mux can be implemented using two 4x1 muxes and one 2x1 mux. 4 of the inputs can first be decoded using each 4-input mux using two l...

As we know, the logical equation of a 2-input XNOR gate is given as below:                       Y = A (xnor) B = (A' B '   +    ...

As we know, the logical equation of a 2-input mux is given as below:                       Y = (s' A   +    s B) Where s is the sele...

As we know, a AND gate's output goes '1' when all its inputs are '1', otherwise it is '0'. The truth table for...

A 3-input XOR gate can be implemented using 2-input XOR gates by cascading 2 2-input XOR gates. Two of the three inputs will feed one of ...

Both NAND and NOR are classified as universal gates, but we see that NAND is preferred over NOR in CMOS logic structures. Let us discus...