VLSI UNIVERSE
Showing posts with label
Clock gating cell
.
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Showing posts with label
Clock gating cell
.
Show all posts
Can we use discrete latches and AND/OR gates instead of ICG?
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In the post, Integated Clock Gating Cell , we discussed that an ICG has a negative level-sensitive latch preceding an AND gate in order to...
Clock gating cell
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Clock gating is a very common technique to save power by stopping the clock to a module when the module is not operating. As discussed in ...
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