VLSI UNIVERSE
Design basics
Listing the posts related to basics of VLSI design. Please add your feedback
here
as to what more topics we should include here or you can ask directly in
design forum
.
Design quiz : Clock multiply by 2 circuit
Latchup in CMOS devices
Multicycle paths - the architectural perspective
Build a latch using a 2:1 multiplexer
Build a 2-input XOR/XNOR gate using a 2:1 multiplexer
Interesting problem - latches in series
Race Conditions
Setup timing and hold time basics
Design Quiz - BCD multiple by 5 circuit
Carry Look Ahead Adder
Binary multiplier
Binary to thermometer encoder
Power Aware RTL design
Analog to Digital Converter
Implement 3 and 4 variable functions using mux
Digital counters
Transmission gates
Regions of operation of MOS Transistors
Need for clock gating checks - need for glitchless clock propagation
Enhancement and depletion MOSFETs
Depletion MOSFET and negative logic - why it is not possible
Latency and throughput - the two measures of system performance
Delay line based time to digital converter
Bubble errors and bubble error correction
Multiplexers
Implementing logic functions using multiplexers
Reset synchronizers
Why is body connected to ground for all NMOS and not to their respective sources
16x1 mux using 4x1 muxes
Integrated clock gating cell (ICG)
Basics of latch timing
Clock multiply by 2
XOR gate using NAND
3-input gates using 2:1 muxes
No comments:
Post a Comment
Thanks for your valuable inputs/feedbacks. :-)
Home
Subscribe to:
Posts (Atom)
No comments:
Post a Comment
Thanks for your valuable inputs/feedbacks. :-)